Routine inspection of the surface of semiconductor wafers during the fabrication of integrated circuits thereon is commonly carried out by a combination of optical inspection of the entire surface and high-resolution electron beam inspection of suspected spots. Characterization of apparent defects detected during such inspection operation must be correlated with actual faults in the fabricated circuits. Such a correlation is obtained, with respect to any particular fabrication process, by the inclusion of suitable electrical test structures in one or more layers of the wafer. The test structures undergo the same processing as the other circuits and are inspected by the aforementioned means. In addition, however, they are also tested electrically, so as to detect any electrical faults, namely “opens” and “shorts”. The results of the electrical tests are compared with the observations from the inspection operations—to establish correlation. This procedure must be performed at least once whenever a new fabrication process is introduced or even when a process is modified; to this end, an array of test patterns that fills the entire area of a special wafer may be used. Additionally, however, the procedure must be repeated periodically, preferably even for every wafer being fabricated, in order to continuously follow, and possibly monitor, any changes that occur in the fabrication process. To this end, test structures are interspersed between the regular chip patterns—preferably within the scribe-lines.
According to prior art, the electrical testing is done by means of probes that are made to contact suitable conductive pads in the test structures. This method has two major drawbacks: (a) To assure mechanical alignment between the probes and the pads, the latter must be made relatively large, thus taking valuable “real estate” from the wafer. (b) The wafer must be placed in the contact-testing device, which is separate from the inspection device, thus incurring extra time and labor. These drawbacks are particularly significant for routine monitoring operation.
More recently, electrical testing by means of an electron beam has come into practice, as disclosed for example in U.S. Pat. No. 5,959,459 and European Patent WO 01/80304. In this method, an electron-beam device, such as a scanning electron microscope (SEM) used for high-resolution wafer inspection, is made to first deposit electrical charges at certain points of a test pattern (usually provided with suitable pads), which charges either remain in the respective circuit elements or are dissipated to ground. The electron-beam device is then made to scan the pattern in a so-called voltage contrast mode, whereby electrons are variously emitted from the surface according to the voltages thereon and collected, to form a sensing current. The latter is then processed to form a so-called voltage-contrast image, which is subsequently interpreted to indicate shorts and opens in the corresponding circuit elements. This method largely overcomes the drawbacks of the contact testing method, enumerated above, in that the pads may be made appreciably smaller and in that the same electron-beam device (namely a SEM) may be used for both electrical testing and inspection for defects.
In prior-art systems that utilize electron beam devices for electrical testing of test structures, scanning of a particular pattern, during both the charging phase and the sensing phase, extends essentially over the entire width of the pattern along one of the two coordinate axes; scanning along the other axis, which necessarily involves mechanical motion, is inherently slow. Moreover, in order to make it reasonably fast, the scanning path is usually linear; this constrains the design of the test structure, and in particular impedes compactness.
Thus there is a clear need for a compact class of test structures and for a method for fast electrical testing of such structures on wafers, utilizing scanning charged-particle beam devices, such as a scanning electron-beam microscope.